The latency and the throughput of the various instructions executed by a processor ultimately determine its performance. Pipelining in a processor is a technique where multiple instructions are overlapped in execution. Rather than processing each instruction sequentially by finishing one instruction before starting the next, each instruction is split into a sequence of steps which can be executed concurrently and in parallel. Pipelining increases instruction throughput by performing multiple operations concurrently but does not reduce latency, which is the time to complete a single instruction from start to finish.
The embodiments described below are provided by way of example only and are not limiting of implementations which solve any or all of the disadvantages of known processors.